1. Field of the Invention
The present invention relates to a technology for analyzing delay in a circuit.
2. Description of the Related Art
With recent development of high-speed-operation (higher-frequency-operation) semiconductor devices, accuracy in signal propagation time in a circuit has become very important. However, a delay serious enough to cause a defective operation can occur in a circuit, due to problems relating to the circuit itself, to manufacturing, or to deterioration. To solve problems in the circuit caused by such delay, it is necessary to take a countermeasure to a cause of the delay in a designing stage or a manufacturing stage.
For example, in a conventional analysis method, since a delay failure test is performed in a scan test on a scan-designed circuit, a flip-flop circuit taking in an error signal can be identified from a fail value. By repeating tracing and verification on an activated path between identified flip-flop circuit and a flip-flop circuit located at the preceding stage, investigation on a failure is performed (for example, Japanese Patent Application Laid-Open Publication No. 2004-85333).
In the above conventional method, it can be found that a delay failure path exists on the path between flip-flop circuits activated when data is set. However, depending on a scale of a combinational circuit in a section between the flip-flop circuits, a huge amount of analysis time is required. If the analysis is left to a user, a result of the analysis varies depending on experience and skill of the user. As a result, accuracy and credibility of the analysis are degraded.